High speed pipelined parallel Huffman decoding

This paper introduces a new class of Huffman decoders which is a development of the parallel Huffman decoder model. With pipelining and partitioning, a regular architecture with an arbitrary degree of pipelining is developed. The proposed architecture dramatically reduces the symbol decoder requirements compared to previous results, and still is the actual implementation of the symbol decoder not treated. The proposed architectures also have a potential of realizing high speed, low power Huffman decoders