DocumentCode :
2309995
Title :
A Pollution Alleviative L2 Cache Replacement Policy for Chip Multiprocessor Architecture
Author :
Zhang, Jun ; Fan, Xiaoya ; Song-He Liu
Author_Institution :
Coll. of Comput. Sci., Northwestern Polytech. Univ., Xi´´an
fYear :
2008
fDate :
12-14 June 2008
Firstpage :
310
Lastpage :
316
Abstract :
Chip multi-processor exploits both instruction-level and thread-level parallelism effectively. In a typical chip multi-processor architecture, L2 cache is shared by multiple cores. Sharing the L2 cache allows high cache utilization and avoids duplicating cache hardware resources. Unfortunately, the mis-predictions of any processor core could lead the load miss from the wrong path to write some useless data into the shared L2 cache, and cause L2 cache pollution. This may increase additional cache misses and lessen performance of other threads for failing to occupy sufficient L2 cache space, and even cause threads starvation. This paper proposes a light pollution replacement policy for shared L2 cache, called LPR, which priorities swapping of wrong path data to eliminate the pollution caused by the execution of the wrong path load instructions as soon as possible. Under the configuration of dual-core CMP architecture, 32KB private data/instruction L1 cache, 512KB shared L2 cache, simulation results show that LPR improves the IPC from 1.83% to 7.57% averagely, 11.1% mostly, and increases the L2 cache hit rate from 0.47% to 0.85% averagely, 1.91% mostly, due to the pollution alleviation of the shared L2 cache.
Keywords :
cache storage; computer architecture; microprocessor chips; multiprocessing systems; L2 cache; cache utilization; chip multiprocessor architecture; dual-core CMP architecture; instruction-level parallelism; light pollution replacement policy; thread-level parallelism; wrong path load instruction; Cache storage; Computer architecture; Computer science; Educational institutions; Hardware; Helium; Parallel processing; Surface-mount technology; Urban pollution; Yarn; Cache; Chip Multi-processor; Replacement policy;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Networking, Architecture, and Storage, 2008. NAS '08. International Conference on
Conference_Location :
Chongqing
Print_ISBN :
978-0-7695-3187-8
Type :
conf
DOI :
10.1109/NAS.2008.30
Filename :
4579608
Link To Document :
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