Analysis of pools of processors with hierarchical bus structure

Author

Chande, P.K. ; Tokekar, S.V. ; Ramani, A.K.

Author_Institution

Dept. of Comput. Sci., SGSITS, Indore, India

fYear

1990

fDate

24-27 Sep 1990

Firstpage

299

Abstract

The authors consider a multiprocessor network, having pools of processing elements (PEs) interconnected with a hierarchical bus structure, suitable for real-time process control applications. The modeling, analysis and performance evaluation of such a network having three hierarchical levels is presented. The access patterns at different hierarchical levels are prioritized and access times are generalized to enable study of different connection time patterns. A semi-Markov process is developed to characterize the behavior of the network. The input parameters to the model are detailed. The different levels of interprocessor communication are parameterized and the various performance measures obtained are given. The analytical results are validated with simulation and the deviation observed was within 9% of simulation

Keywords

Markov processes; multiprocessor interconnection networks; performance evaluation; process computers; real-time systems; access patterns; connection time patterns; hierarchical bus structure; interprocessor communication; multiprocessor network; performance evaluation; processing element pools; real-time process control applications; semi-Markov process; Analytical models; Application software; Bandwidth; Computer science; Length measurement; Multiprocessing systems; Performance analysis; Process control; Real time systems; Time measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer and Communication Systems, 1990. IEEE TENCON'90., 1990 IEEE Region 10 Conference on

Print_ISBN

0-87942-556-3

Type

conf

DOI

10.1109/TENCON.1990.152620

Filename

152620