Title :
ULSI-quality gate oxide on thin-film-silicon-on-insulator
Author :
Huang, W.M. ; Ma, Z.J. ; Racanelli, M. ; Hughes, D. ; Ajuria, S. ; Huffman, G. ; Ong, T.P. ; Ko, P.K. ; Hu, C. ; Hwang, B.Y.
Author_Institution :
Adv. Custom Technol., Motorola Inc., Mesa, AZ, USA
Abstract :
Gate oxide quality for sub-0.5 /spl mu/m applications on Thin-Film-Silicon-On-Insulator (TFSOI) substrates is described. Intrinsic thermal oxide properties such as I-V, Q/sub BD/ and charge trapping rates, as well as device effective mobilities, of TFSOI are comparable to bulk. However, increased surface micro-roughness on SOI materials leads to a higher thermal oxide defect density relative to that of bulk silicon. The use of wafer polish or stacked thermal/LPCVD oxide is found to be effective in achieving bulk-quality oxide defect densities on TFSOI while maintaining intrinsic I-V, Q/sub BD/ and charge trapping properties.<>
Keywords :
CMOS integrated circuits; SIMOX; VLSI; carrier mobility; electron traps; integrated circuit technology; polishing; semiconductor-insulator boundaries; silicon; 0.5 micron; CMOS process; TFSOI; ULSI-quality gate oxide; bulk-quality oxide defect densities; charge trapping rates; device effective mobilities; gate oxide quality; stacked thermal/LPCVD oxide; surface micro-roughness; thermal oxide defect density; thermal oxide properties; thin-film-silicon-on-insulator; wafer polish; Capacitors; Design for quality; Electric breakdown; MOS devices; Oxidation; Rough surfaces; Silicon; Substrates; Surface treatment; Testing;
Conference_Titel :
Electron Devices Meeting, 1993. IEDM '93. Technical Digest., International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-1450-6
DOI :
10.1109/IEDM.1993.347208
