Title :
On the design of robust testable CMOS combinational logic circuits
Author :
Kundu, S. ; Reddy, S.M.
Author_Institution :
Dept. of Electr. & Comput. Eng., Iowa Univ., IA, USA
Abstract :
The authors propose an integrated approach to the design of combinational logic circuits in which stuck-open faults and path delay faults are detectable by robust tests that detect modeled faults independent of the delays in the circuit under test. They demonstrate that the proposed designs and tests guarantee the design of CMOS logic circuits in which all path delay faults are locatable.<>
Keywords :
CMOS integrated circuits; combinatorial circuits; logic design; logic testing; design; path delay faults; robust testable CMOS combinational logic circuits; stuck-open faults; CMOS logic circuits; Circuit faults; Circuit testing; Combinational circuits; Delay; Electrical fault detection; Fault detection; Logic testing; Robustness; Semiconductor device modeling;
Conference_Titel :
Fault-Tolerant Computing, 1988. FTCS-18, Digest of Papers., Eighteenth International Symposium on
Conference_Location :
Tokyo, Japan
Print_ISBN :
0-8186-0867-6
DOI :
10.1109/FTCS.1988.5323
