A VLSI grammar processing subsystem for a real time large vocabulary continuous speech recognition system

Author

Chen, D. ; Yu, R. ; Rabaey, J. ; Brodersen, R.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

fYear

1990

fDate

13-16 May 1990

Abstract

The architecture and implementation of a grammar processing subsystem for a large vocabulary, real-time, continuous speech recognition system are summarized. This subsystem contains two custom VLSI chips which perform the evaluation of starting word probabilities associated with the across-word transitions in the hidden-Markov-model-based speech recognition system. This system has a maximum computation rate of 200 MOPS and an I/O bandwidth of 265 Mbyte/s. The recognized sentence is the sentence with the highest combined acoustic and language model probabilities

Keywords

CMOS integrated circuits; VLSI; digital signal processing chips; real-time systems; speech analysis and processing; speech recognition; 265 Mbyte/s; CMOS; I/O bandwidth of 265 Mbyte/s; across-word transitions; architecture; computation rate; custom VLSI chips; evaluation of starting word probabilities; grammar processing subsystem; hidden-Markov-model-based speech recognition system; implementation; large vocabulary continuous speech recognition system; real-time speech recognition system; Application specific integrated circuits; Hidden Markov models; Probability; Real time systems; Speech processing; Speech recognition; Text processing; Very large scale integration; Vocabulary;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990

Conference_Location

Boston, MA

Type

conf

DOI

10.1109/CICC.1990.124726

Filename

124726