Title :
A 40-MHz encoder-decoder chip generated by a Reed-Solomon code compiler
Author_Institution :
LSI Logic Corp., Menlo Park, CA
Abstract :
An eight-error correcting Reed-Solomon (RS) encoder-decoder chip is presented. The encoder and decoder can independently process 40 Mbytes of data per second. The design was generated by an RS code compiler. The chip, fabricated in a 1-μm CMOS compacted-array technology with a 9.5-mm×9.5-mm die, has been tested and is fully functional. The RS code has symbol size 8 (1 byte/symbol). It has 16 bytes of redundancy and corrects 8 bytes of errors per codeword. The code length (between 54 and 255 bytes inclusive) is selectable by the user
Keywords :
CMOS integrated circuits; VLSI; codecs; digital signal processing chips; encoding; error correction; logic arrays; redundancy; 1 micron; 40 MHz; 40 Mbyte/s; 8 error correcting chip; 9.5 mm; CMOS compacted-array technology; RS code compiler; Reed-Solomon code compiler; encoder-decoder chip; redundancy; Application specific integrated circuits; CMOS technology; Decoding; Encoding; Error correction codes; Galois fields; Polynomials; Redundancy; Reed-Solomon codes; Testing;
Conference_Titel :
Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990
Conference_Location :
Boston, MA
DOI :
10.1109/CICC.1990.124728
