A capacitorless DRAM cell on SOI substrate

Author

Hsing-jen Wann ; Chenming Hu

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

fYear

1993

fDate

5-8 Dec. 1993

Firstpage

635

Lastpage

638

Abstract

We propose a capacitorless DRAM (CDRAM) cell on SOI substrate with large READ current (>100 /spl mu/Aspl mu/m), small cell size, and simple fabrication process. PISCES simulations are used to analyze the memory cell operations. The CDRAM cell size is that of a transistor, which makes it very attractive for high density memory applications. Since the fabrication process of CDRAM is compatible with that of the general purpose SOI CMOS and complementary BiCMOS process, CDRAM can also be used for integrated on-chip memory and is an interesting candidate as the technology driver of SOI VLSI.<>

Keywords

BiCMOS integrated circuits; CMOS integrated circuits; DRAM chips; VLSI; cellular arrays; digital simulation; integrated circuit technology; semiconductor-insulator boundaries; silicon; CDRAM cell; CMOS; PISCES simulations; SOI VLSI; SOI substrate; capacitorless DRAM cell; cell size; complementary BiCMOS; fabrication process; high density memory application; integrated on-chip memory; CMOS technology; Capacitance; Capacitors; Driver circuits; Fabrication; Isolation technology; MOSFET circuits; Manufacturing processes; Random access memory; Substrates;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1993. IEDM '93. Technical Digest., International

Conference_Location

Washington, DC, USA

ISSN

0163-1918

Print_ISBN

0-7803-1450-6

Type

conf

DOI

10.1109/IEDM.1993.347280

Filename

347280