Title :
A novel method to determine gate-drain overlap in sub-micron transistors
Author :
Duvvury, Charvaka ; Wise, J.L. ; Machala, C.F. ; Yang, P.
Author_Institution :
Semicond. Process & Design Center, Texas Instrum. Inc., Dallas, TX, USA
Abstract :
This paper describes a novel method to determine the gate-drain overlap in a sub-micron channel length transistor under circuit operating conditions. The method essentially entails applying 500 ns wide square wave pulses to the MOSFET drain and measuring the drain current response as determined by the gate coupling which, in turn, is determined by the gate-drain overlap capacitance. After obtaining an accurate DC current model, the pulse measurements are matched with SPICE simulations to determine the accurate value for total lateral diffusion.<>
Keywords :
insulated gate field effect transistors; 500 ns; DC current model; MOSFET; SPICE simulations; circuit operating conditions; drain current; gate coupling; gate-drain overlap capacitance; lateral diffusion; pulse measurements; square wave pulses; sub-micron channel length transistor; CMOS technology; Capacitance measurement; Circuits; Current measurement; Diodes; MOSFETs; Parasitic capacitance; Pulse measurements; SPICE; Semiconductor process modeling;
Conference_Titel :
Electron Devices Meeting, 1993. IEDM '93. Technical Digest., International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-1450-6
DOI :
10.1109/IEDM.1993.347304