• DocumentCode
    2316686
  • Title

    High speed 0.55 micron BiCMOS family of ASICs

  • Author

    Mehta, Yeshwant ; Wong, Tony ; Tam, Anna

  • Author_Institution
    LSI Logic Corp., Milpitas, CA, USA
  • fYear
    1990
  • fDate
    13-16 May 1990
  • Abstract
    A BiCMOS family of ASICs with 290 ps delay, 0.55 μm Leff N (channel), complexity of 120000 to 200000 equivalent used gates, TTL/CMOS/ECL interface, up to 72 mA output drive capability, and multiport RAMs and ROMs is described. The trade-offs between CMOS and BiCMOS are discussed. The three different methodologies, cell-based, array-based, and embedded array, are compared. The features for these technologies are highlighted. Using this technology a user can build high-performance systems on a chip
  • Keywords
    BIMOS integrated circuits; VLSI; application specific integrated circuits; cellular arrays; digital integrated circuits; integrated circuit technology; 0.55 micron; 290 ps; 72 mA; BiCMOS family of ASICs; CMOS/BiCMOS tradeoffs; ROMs; TTL/CMOS/ECL interface; VLSI; array based ASIC; cell based ASIC; embedded array; multiport RAMs; output drive capability; trade-offs; Application specific integrated circuits; BiCMOS integrated circuits; CMOS logic circuits; CMOS technology; Delay effects; Large scale integration; Noise reduction; Read only memory; Semiconductor device modeling; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990
  • Conference_Location
    Boston, MA
  • Type

    conf

  • DOI
    10.1109/CICC.1990.124751
  • Filename
    124751
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2316686