Title :
A chip-set for lossless image compression
Author :
Shah, Imran ; Akiwumi-Assani, Olu ; Johnson, Brian
Author_Institution :
North American Philips Corp., Briarcliff Manor, NY, USA
Abstract :
Two chips have been developed for lossless image compression. The first IC performs a transformation, and the second performs lossless coding. This work presents the transform and coding algorithms and the main architectural features of the chips, and outlines some performance specifications. The image compression/decompression system described reduces storage requirements in high-speed image archival and database applications and speeds the transmission of digital images over communication channels
Keywords :
CMOS integrated circuits; PACS; VLSI; application specific integrated circuits; bandwidth compression; computerised picture processing; data compression; architectural features; chip-set; coding algorithms; hierarchical transformation; high-speed image archival; high-speed image database applications; image compression/decompression system; lossless coding chip; lossless image compression; performance specifications; reduces storage requirements; transform algorithms; transformation chip; transmission of digital images; two-chip set; Application specific integrated circuits; Clocks; Codecs; Computer architecture; DH-HEMTs; Entropy coding; Frequency; Image coding; Pipelines; Pixel;
Conference_Titel :
Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990
Conference_Location :
Boston, MA
DOI :
10.1109/CICC.1990.124764
