High switching frequency DSP controlled PWM inverter

A new algorithm of the deadbeat controlled PWM inverter operating at high switching frequency is presented. Two-level switching patterns are applied to a half-bridge inverter. This scheme allows the use of higher switching frequency for a given computation time delay, which results in lower harmonic distortion at the output. For a PWM inverter, the best performance is obtained by operating the inverter at the highest possible switching frequency. An algorithm computing the switching pattern to be implemented in the next interval is also investigated and compared with the algorithm computing the switching pattern to be implemented in the current interval. Computer simulations and experimental results are presented