DocumentCode
231981
Title
The design of HIMAC coprocessor based on HINOC 2.0
Author
Deng Chen ; Weitao Pan ; Jinyuan Zhang ; Chun Liu ; Zhiliang Qiu ; Shi Zhang ; Bing Zhang ; Chun Yang ; Cheng Zhang
Author_Institution
State Key Lab. of Integrated Services Networks, Xidian Univ., Xian, China
fYear
2014
fDate
19-23 Oct. 2014
Firstpage
1618
Lastpage
1621
Abstract
In this paper, we introduced a hardware acceleration coprocessor design of HIMAC 2.0 in HINOC 2.0 system. The main function of HIMAC 2.0 have been detailed and compared with corresponding part of HINOC 1.0. By building the self-testing platform and designing the test scheme, the design, which has been simulated and has passed the FPGA verification, realizes 1Gbps data transmission between HIMAC 2.0 and Ethernet.
Keywords
coprocessors; field programmable gate arrays; local area networks; logic design; Ethernet; FPGA; HIMAC 2.0; HINOC 1.0; HINOC 2.0; data transmission; hardware acceleration coprocessor design; Acceleration; Buffer storage; Coprocessors; Field programmable gate arrays; Hardware; Media Access Protocol; Random access memory; FPGA; HIMAC; HINOC;
fLanguage
English
Publisher
ieee
Conference_Titel
Signal Processing (ICSP), 2014 12th International Conference on
Conference_Location
Hangzhou
ISSN
2164-5221
Print_ISBN
978-1-4799-2188-1
Type
conf
DOI
10.1109/ICOSP.2014.7015269
Filename
7015269
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