Impact of varying processor number for H264 in FPGA platform

Author

Feki, O. ; Loukil, H. ; Ben Atitallah, A. ; Masmoudi, N.

Author_Institution

Nat. Sch. of Eng., Univ. of Sfax, Sfax, Tunisia

fYear

2010

fDate

27-30 June 2010

Firstpage

1

Lastpage

5

Abstract

Multiprocessor architecture can be a solution to meet the increasing computational requirements for multimedia treatment algorithms such as video encoding. In this paper we study the effect of varying the processors number on resource utilization and system performance. We used Altera´s NIOS II processors interconnected through Avalon bus. We vary the processors number from one to four and note its effect on the use of logic elements, DSP blocks and memory bits. We also note the change of the time execution of the Intra 16×16 chain of the H264/AVC encoder.

Keywords

digital signal processing chips; field programmable gate arrays; multimedia computing; multiprocessing systems; resource allocation; video coding; video discs; Altera´s NIOS II processors; Avalon bus; DSP blocks; FPGA platform; H264/AVC encoder; logic elements; multimedia treatment algorithm; multiprocessor architecture; resource utilization; video encoding; Computer architecture; SDRAM; H.264/AVC; Multiprocessor; NIOS II; intra16×16;

fLanguage

English

Publisher

ieee

Conference_Titel

Systems Signals and Devices (SSD), 2010 7th International Multi-Conference on

Conference_Location

Amman

Print_ISBN

978-1-4244-7532-2

Type

conf

DOI

10.1109/SSD.2010.5585523

Filename

5585523