Low Power Cordic IP Core Implementation

There is a high demand for low power and efficient implementation of complex arithmetic operations in many digital signal processing (DSP) algorithms. The CORDIC algorithm is suitable to be implemented in DSP systems since its calculation for complex arithmetic is simple and elegant. However, the large number of iterations involved in CORDIC operation limits its speed performance seriously and also consumes large power. This paper presents three CORDIC IP cores which were implemented using a new CORDIC algorithm. Each of them has one or more distinctive performances in terms of power, area, speed and flexibility due to their different architectures