Title :
A 2.5 ns ECL 16×16 multiplier
Author :
Roberts, Scott ; Snyder, Warren ; Chin, Howey ; Hingarh, Hem ; Leibiger, Steve ; Lahri, Rajeeva ; Bouknight, Lyle ; Biswal, Madan
Author_Institution :
Nat. Semicond., Puyallup, WA, USA
Abstract :
A 16×16 b integer multiplier is described that has achieved a measured delay of less than 2.5 ns, register to register, for a full 16×16 multiply. It was fabricated using ASPECT 3, a 0.8 μm bipolar process with silicided polysilicon and four-level metallization. A standard cell methodology using an automated sizing and scaling approach was used. In register-to-register mode the worst case clock period is 2.495 ns, with a measured pin-to-pin flow thru mode latency time of 3.37 ns. The I/O delay plus register setup is 875 ps
Keywords :
bipolar integrated circuits; emitter-coupled logic; integrated logic circuits; multiplying circuits; 0.8 micron; 2.5 ns; ASPECT 3; ECL; automated sizing; bipolar process; four-level metallization; integer multiplier; register-to-register mode; silicided polysilicon; standard cell methodology; Adders; Application specific integrated circuits; Circuit synthesis; Delay; Latches; Logic arrays; Logic circuits; Logic design; Pipelines; Registers;
Conference_Titel :
Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990
Conference_Location :
Boston, MA
DOI :
10.1109/CICC.1990.124791
