A new VLSI architecture for a reconfigurable, high-speed, digital Rank Order Filter

A new architecture to realize a moduler, high-speed, reconfigurable, digital rank order filter (ROF) is presented in this paper. A bit-level algorithm by Kar and Pradhan has been modified in this work to implement the proposed rank order filter. Using the proposed digital rank selection circuit it is possible to find the element of a certain rank in a given sequence of N elements in each window in M steps, where M is the number of bits used in binary representation for the elements of the sequence. To implement the algorithm N number of identical bit update circuit (BUC), a parallel counter circuit and a comparator circuit is required. Using parallel processing technique such as data pipelining and block processing the throughput of the circuit could be increased by M times. The performance of the filter was found better in terms of speed, power consumption and reliability.