Title :
Utilization of Rams With a Defective Row or Column In Micros and Minis
Author_Institution :
Iowa State University
Keywords :
Clocks; Content addressable storage; Costs; Delay; Integrated circuit yield; PROM; Pins; Random access memory; Read-write memory; Timing;
Conference_Titel :
Compcon Fall 79. Proceedings
DOI :
10.1109/CMPCON.1979.729147
