Low-jitter PLL by interpolate compensation

In order to reduce jitters, vital characteristics in some PLL applications, a PLL with compensator and interpolative loop is proposed. This PLL improves the problem that conventional PLL cannot detect jitters at the time other than the reference input. AS a result, it reduces jitters as frequency synthesizers with high multiplication ratios. We tailored the circuit to improve responsiveness, as well. The effectiveness is verified on a prototype implemented in a Cyclone FPGA, and experiments as a mutiply-by-50 synthesizer results in 30-fold reduction in two jitter measures.