Title :
A multiplication-free parallel architecture for affine transformation
Author :
Badawy, Wael ; Bayoumi, Magdy
Author_Institution :
Center for Adv. Comput. Studies, Louisiana Univ., Lafayette, LA, USA
Abstract :
This paper presents a novel low power parallel architecture for computing affine transformation (AT). It is based on a new multiplication-free algorithm that employs the inherent algebraic properties of the AT. Low power has been achieved at the algorithmic level by replacing the multiplication with shifting operation, at the architecture level by using parallel computational units, and at the circuit level by using low power cells. The proposed architecture can be used as a computational kernel in object-based video processing. It is compatible with MPEG-4 and VRML standards. The architecture has been prototyped in 0.6 μm CMOS technology with three layers of metal
Keywords :
CMOS digital integrated circuits; data compression; low-power electronics; motion compensation; object-oriented methods; parallel architectures; video coding; 0.6 micron; CMOS technology; MPEG-4; VRML; affine transformation; architecture level; circuit level; computational kernel; low power cells; multiplication-free parallel architecture; object-based video processing; parallel computational units; shifting operation; Batteries; CMOS technology; Computer architecture; Concurrent computing; Equations; Kernel; MPEG 4 Standard; Motion compensation; Parallel architectures; Video compression;
Conference_Titel :
Application-Specific Systems, Architectures, and Processors, 2000. Proceedings. IEEE International Conference on
Conference_Location :
Boston, MA
Print_ISBN :
0-7695-0716-6
DOI :
10.1109/ASAP.2000.862375
