The design of a bit-serial coprocessor to perform multiplication and division on a massively parallel architecture

The design of a VLSI coprocessor element (COPE) that uses a parallel adder to achieve the increased speed needed by the many multiplications and divisions required by fast Fourier transforms (FFTs), convolutions, and other common operations is discussed. It accepts operands of variable length (N⩽16), and produces a 2N bit product. The overall process takes 4N cycles, and the result can be accumulated for further processing without any processing time penalty. In addition, the COPE is designed to perform division in O(4N) cycles, as opposed to O(N²) for a conventional bit serial processor. A description of the simple hardware architecture is presented, followed by the algorithms used for multiplication and division. Performance comparisons between the algorithms used in the COPE, distributed array processor (DAP), and geometric arithmetic parallel processor (GAPP) for multiplication, division, and multiply-accumulate operations are given