Title :
Labyrinth: a homogeneous computational medium
Author :
Furtek, Frederick ; Stone, Glen ; Jones, Ian
Author_Institution :
Concurrent Logic Inc., Arlington, MA, USA
Abstract :
As a RAM-based reconfigurable logic array, Labyrinth provides the flexibility and malleability of software with the performance of a dedicated circuit. With a single bit register and a half adder per cell, the architecture is optimized for register intensive, massively parallel algorithms. The fine-grained, highly-symmetric architecture scales very naturally and facilitates compact circuit layouts. A 64-cell test chip has been successfully built and tested, and a 4096-cell chip is in the final stages of preparation for fabrication
Keywords :
CMOS integrated circuits; logic arrays; microprocessor chips; parallel architectures; 4096-cell chip; 64-cell test chip; Labyrinth; PLD; RAM-based reconfigurable logic array; compact circuit layouts; half adder per cell; highly-symmetric architecture; homogeneous computational medium; massively parallel algorithms; programmable logic devices; single bit register; Adders; Circuit testing; Computer architecture; Fabrication; Flexible printed circuits; Logic arrays; Parallel algorithms; Reconfigurable logic; Registers; Software performance;
Conference_Titel :
Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990
Conference_Location :
Boston, MA
DOI :
10.1109/CICC.1990.124839
