An ultrahigh-speed full adder using resonant-tunneling logic gates

Author

Waho, Takao ; Okuyama, Hiroki ; Ebata, Tomohiko ; Kato, Ryousuke

Author_Institution

Fac. of Sci. & Technol., Sophia Univ., Tokyo

fYear

2008

fDate

Nov. 30 2008-Dec. 3 2008

Firstpage

1724

Lastpage

1727

Abstract

An ultrahigh-speed full adder using resonant-tunneling diodes (RTDs) has been investigated by circuit simulation. The adder uses NOR logic gates, each of which consists of four RTDs (called 4RTD logic gate), with a four-phase pipelined scheme. Circuit simulation has been carried out by assuming an InP-based RTD device model, the peak current density and the peak-to-valley ratio of which are 5.0 times 10⁵ A/cm² and 10, respectively. The simulation shows that the full adder operates at a clock frequency as high as 50 GHz.

Keywords

III-V semiconductors; adders; circuit simulation; indium compounds; logic gates; resonant tunnelling diodes; InP; NOR logic gates; RTD device model; circuit simulation; four-phase pipelined scheme; peak current density; peak-to-valley ratio; resonant-tunneling diodes; resonant-tunneling logic gates; ultrahigh-speed full adder; Adders; Circuit simulation; Clocks; Current density; Logic circuits; Logic devices; Logic gates; Resonant tunneling devices; Switches; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2008. APCCAS 2008. IEEE Asia Pacific Conference on

Conference_Location

Macao

Print_ISBN

978-1-4244-2341-5

Electronic_ISBN

978-1-4244-2342-2

Type

conf

DOI

10.1109/APCCAS.2008.4746372

Filename

4746372