DocumentCode :
2330756
Title :
A new modulo-N based digital clock synthesizer with an adjustable duty-cycle
Author :
Chen, Chen-Feng ; Huang, Jiun-Jia ; Chau, Yawgeng A.
Author_Institution :
Dept. of Commun. Eng., Yuan Ze Univ., Chung-Li
fYear :
2008
fDate :
Nov. 30 2008-Dec. 3 2008
Firstpage :
1798
Lastpage :
1801
Abstract :
A new architecture of digital clock synthesizer with an adjustable duty-cycle is designed. In the new architecture, a set of reference clocks with the same frequency but different phases is passed through a multiplexer (Mux) that is combined with an incrementer to output the maximal frequency to a modulo-N counter, where two frequency control words (FCWs) are used for the duty-cycle setting. A Gray encoder is designed to eliminate the glitch problem of the multiplexer. The function and performance of the synthesizer are validated via implementation and timing simulations with the TSMC 0.18 mum cell-based library.
Keywords :
clocks; frequency synthesizers; multiplexing equipment; network synthesis; thyristor applications; Gray encoders; TSMC; adjustable duty-cycle; digital clock synthesizer; duty-cycle setting; frequency control words; glitch problem; incrementer; modulo-N counter; multiplexer; timing simulations; Arithmetic; Clocks; Counting circuits; Energy consumption; Frequency control; Frequency synthesizers; Libraries; Multiplexing; Signal design; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2008. APCCAS 2008. IEEE Asia Pacific Conference on
Conference_Location :
Macao
Print_ISBN :
978-1-4244-2341-5
Electronic_ISBN :
978-1-4244-2342-2
Type :
conf
DOI :
10.1109/APCCAS.2008.4746391
Filename :
4746391
Link To Document :
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