• DocumentCode
    2331162
  • Title

    A methodology for fast and accurate yield factor estimation during global routing

  • Author

    Sinha, Subarna ; Chiang, Charles C.

  • Author_Institution
    Synopsys Inc., Mountain View
  • fYear
    2007
  • fDate
    4-8 Nov. 2007
  • Firstpage
    481
  • Lastpage
    487
  • Abstract
    In this paper, a novel and computationally efficient methodology to accurately estimate key yield factors during the global routing stage is presented. Such an yield factor estimator at the global routing stage is essential since it can used to either get an early estimate of the final yield of the same design (i.e. the yield after applying the required sequence of detailed routing and post-routing yield optimizations) and/or to improve the final yield of the design by making the solution at the end of global routing more amenable to post-routing yield optimizations. The proposed yield factor estimator is inherently flexible and can easily be programmed to estimate during global routing a variety of key yield factors of the same design after a typical sequence of detailed routing and representative post-routing yield optimizations has been applied. Examples are provided to show how the yield factor estimator can be used to predict short and open critical area and metal density after typical yield optimization solutions like wire-spreading, wire-widening and metal filling, respectively. Experimental results presented in the paper show that the proposed yield factor estimator can predict final yield factor hotspots/values with a high degree of accuracy. The proposed estimator is also shown to be more suited for the purpose of yield factor estimation compared with typical metrics at the global routing stage like congestion.
  • Keywords
    VLSI; circuit optimisation; design for manufacture; estimation theory; integrated circuit design; integrated circuit manufacture; integrated circuit yield; network routing; GRYP yield factor estimator; VLSI technology; global routing yield predictor; integrated circuit design; post-routing yield optimizations; Chemicals; Contamination; Design optimization; Filling; Lithography; Manufacturing; Routing; Very large scale integration; Wires; Yield estimation;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer-Aided Design, 2007. ICCAD 2007. IEEE/ACM International Conference on
  • Conference_Location
    San Jose, CA
  • ISSN
    1092-3152
  • Print_ISBN
    978-1-4244-1381-2
  • Electronic_ISBN
    1092-3152
  • Type

    conf

  • DOI
    10.1109/ICCAD.2007.4397311
  • Filename
    4397311