• DocumentCode
    2332956
  • Title

    Maximizing transducer gain per power dissipation in 100 GHz CMOS six-stage amplifier

  • Author

    Suizu, Masafumi ; Katayama, Kosuke ; Motoyoshi, Mizuki ; Takano, Kyoya ; Fujishima, Minoru

  • Author_Institution
    Sch. of Eng., Hiroshima Univ., Higashi-Hiroshima, Japan
  • fYear
    2012
  • fDate
    9-11 May 2012
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    In this paper we propose a method of maximizing the efficiency, defined as transducer gain GT per power dissipation PDC, of a CMOS 100 GHz six-stage amplifier using bias point tuning. Using this method, the optimal bias voltage was 0.75V and the efficiency was 30dB/W higher than that for a voltage of 0.9V.
  • Keywords
    CMOS integrated circuits; amplifiers; CMOS six-stage amplifier; bias point tuning; frequency 100 GHz; optimal bias voltage; power dissipation; transducer gain; voltage 0.75 V; voltage 0.9 V; CMOS integrated circuits; Educational institutions; Gain; Power amplifiers; Power demand; Power dissipation; Transducers; Millimeter wave; Power amplifier; Power dissipation; Transceiver; Transducer gain;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Future of Electron Devices, Kansai (IMFEDK), 2012 IEEE International Meeting for
  • Conference_Location
    Osaka
  • Print_ISBN
    978-1-4673-0837-3
  • Type

    conf

  • DOI
    10.1109/IMFEDK.2012.6218631
  • Filename
    6218631
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2332956