Low cost schemes for fault tolerance in matrix opebations with processor abbays

Matrix encoding schemes are proposed to detect and correct errors when matrix operations are performed using processor arrays. The method proposed assumes that failures are confined to a single processor. Such a fault model covers a broad class of faults. This method is not only applicable to errors caused by permanent faults but also to transient errors. Two processor array architectures for matrix multiplication are investigated and compared from a fault-tolerance viewpoint; it is shown that only small redundancy ratios - O(1/n) of hardware and O(log₂(n)/n) of time, are required for processor array systems to achieve reliable matrix operations.