Design and Implementation of High Performance IPSec Applications with Multi-Core Processors

The rapid increasing Internet services need high performance, scalable and flexible network security devices. IPSec is a set of protocols to ensure transmission of packets in IP network. Multi-core processors are targeted to a wide range of applications with complex packet processing and high throughput requirements. Although there are several designs of IPSec system with heterogeneous hardware platforms, practical ultra-speed network security systems remain elementary. The disparity arises because IP network security algorithms with theoretically considerable computational cost and packet processing have unacceptably memory access latency. This paper discusses the design and implementation of IPSec applications at 17 Gbps using next generation programmable multi-core processor RMI XLR732. We focus on IP Security software architecture suitable for high speed network, and present consideration of traffic load balance and hardware framework. The improved software architecture is implemented on the dual multi-core processor hardware, and actual packet data is used to assess performance.