Scalable Test Generation by Interleaving Concrete and Symbolic Execution

Functional validation is widely acknowledged as a major challenge for System-on-Chip (SoC) designs. Directed tests are superior compared to random tests since a significantly less number of directed tests can achieve the same coverage goal. Existing test generation techniques have inherent limitations due to use of formal methods. First, these approaches expect formal specification and do not directly support Hardware Description Language (HDL) models. Most importantly, the complexity of real world designs usually exceeds the capacity of model checking tools. In this paper, we propose a scalable technique to enable directed test generation for HDL models by combining static analysis and simulation based validation. Unlike existing approaches that support a limited set of HDL features, our approach covers a wide variety of features including dynamic array references. We have compared our approach with existing hybrid as well as random test generation techniques using various fault models. Our experimental results demonstrate that our proposed technique is scalable, and enables directed test generation for large designs.