Counter-based residue arithmetic circuit for VLSI digital signal processing systems

The counter-based residue arithmetic circuit, which is composed of ring counters and performs residue arithmetic operations by pulse counting, is proposed for the efficient implementation of VLSI digital signal processing systems. A masterslice LSI on which counter-based residue arithmetic circuits are regularly arranged is also presented. It is demonstrated that the counter-based residue arithmetic circuit has a simple, regular, and well partitioned structure, and that a highly regular and parallel architecture based on both the residue number system and pipelining can be realized