Title :
Process Synchronization in Multi-core Systems Using On-Chip Memories
Author :
Joseph, Alvin ; Dhanwada, Nagu R.
Author_Institution :
IBM Syst. & Technol. Group, Bangalore, India
Abstract :
In this paper, we present a novel process synchronization mechanism and the application of on-chip memories for process synchronization in multi-core systems. The multi-core processor architecture and a signaling scheme which supports the novel process synchronization mechanism are presented. The validity of the proposed synchronization mechanism is demonstrated by experiments on a virtual prototyping platform. Also, comparison against external memory based schemes shows that the proposed use of on-chip memories in multi-core process synchronization is an effective solution to reduce synchronization overheads, especially as the number of processor cores increase.
Keywords :
multiprocessing systems; synchronisation; system-on-chip; virtual prototyping; external memory based scheme; multicore processor architecture; on-chip memory; process synchronization mechanism; signaling scheme; synchronization overhead reduction; virtual prototyping platform; Generators; Memory management; Multicore processing; Receivers; Synchronization; System-on-chip; multi-core; on-chip memories; process synchronization;
Conference_Titel :
VLSI Design and 2014 13th International Conference on Embedded Systems, 2014 27th International Conference on
Conference_Location :
Mumbai
DOI :
10.1109/VLSID.2014.43
