A Novel Architecture for FPGA Implementation of Otsu´s Global Automatic Image Thresholding Algorithm

Otsu´s global automatic image thresholding technique is widely used in various computer vision-based applications. This paper presents a resource-efficient architecture for the design of Otsu´s thresholding algorithm and its implementation in field-programmable gate array (FPGA). The proposed architecture is implemented for a 640x480 size of input image that is captured by a real-time high-resolution analog camera and buffered in a DDR2 SDRAM memory. The computation of between-class variance in Otsu´s algorithm requires the evaluation of a normalized cumulative histogram, mean and cumulative moments, which need single-cycle read-modify-write operations. These operations are achieved by incorporating the FPGA´s slices, dual-port Block RAM memories and DSP slices with DDR2 SDRAM as a frame buffer. The data path of the architecture is fixed-point arithmetic based and it does not require any divider. The proposed design is implemented in Xilinx Virtex-5 xc5vfx70tffg1136-1 FPGA device, available on the Xilinx ML-507 platform. In order to develop the required hardware and software in an integrated method, the Xilinx Embedded Development Kit (EDK) design tool is used.