An Optimized Design of Reversible Quantum Comparator

Reversible computing has emerged as promising technology having its applications in emerging technologies like quantum computing, optical computing etc. This paper presents a reversible comparator based on prefix tree grouping methodology. The proposed design is realized by cascading three stages. The first stage is a 1-bit reversible comparator which generates ´greater´ and ´equal´ signals of that operand bit. These signals are combined using prefix tree grouping logic to generate final ´greater´ and ´equal´ signals. Using these final ´greater´ and ´equal´ signals, ´lesser´ signal is generated in the third stage. The design is optimized in quantum level for efficient performance in all the cost metrics. The proposed 64-bit comparator design results in 14.3% reduced quantum delay, 7.8% reduced quantum cost and 25% reduced garbage outputs when compared with the best existing design of prefix based comparator.