Performance modeling and estimation along an MPSoC flow

We present in this paper, a new approach of heterogeneous multiprocessors systems-on-chip architecture (MPSoC) co-design based on performance control. This approach is centered on the structuring of the models and the levels of abstraction. Four models are proposed permuting to establish the refinement and the control at the time of the passage by six levels of abstraction. An extension of Khanpsilas model, based on the addition of the relative annotations to the times of execution of the parallel threads and to the size of the data exchanged by these threads, is used. Experimentation is achieved, in this context, on the MJPEG decoder and the Virtex II Pro platform of Xilinx.