A low dropout voltage regulator with programmable output

Author

Wu, Ying-Cheng ; Huang, Chun-Yueh ; Liu, Bin-Da

Author_Institution

Dept. of Electron. Eng., Nat. Univ. of Tainan, Tainan, Taiwan

fYear

2009

fDate

25-27 May 2009

Firstpage

3357

Lastpage

3361

Abstract

In this paper, we present a low dropout voltage regulator (LDO) which can be programmed to generate four output voltages (3.3 V, 2.5 V, 1.8 V, and 0 V) by the external control signals. Between the error amplifier and the power transistor, we place a simple buffer so that the power supply rejection (PSR) of LDO can be improved. The design specification of the maximum load current is 100 mA. The proposed LDO is designed by the 0.35 mum CMOS 2P4M process technology and simulated by HSPICE. Simulation results show that the maximum transient-output variation (overshoot voltage) is about 50 mV with full-load step change of 100 mA and the PSR is larger than 60 dB for different output voltages. Therefore, the proposed LDO can be applied for power management systems in system-on-chip (SOC), where the output voltage can be changed by control logic to optimize the power consumption of supplied device.

Keywords

CMOS integrated circuits; system-on-chip; voltage regulators; CMOS process; HSPICE simulation; current 100 mA; error amplifier; low dropout voltage regulator; power management systems; power supply rejection; power transistor; size 0.35 mum; system-on-chip; voltage 0 V to 3.3 V; CMOS process; CMOS technology; Energy management; Low voltage; Power amplifiers; Power supplies; Power transistors; Regulators; Signal generators; Voltage control; dc-dc convertor; low dropout liner regulator;

fLanguage

English

Publisher

ieee

Conference_Titel

Industrial Electronics and Applications, 2009. ICIEA 2009. 4th IEEE Conference on

Conference_Location

Xi´an

Print_ISBN

978-1-4244-2799-4

Electronic_ISBN

978-1-4244-2800-7

Type

conf

DOI

10.1109/ICIEA.2009.5138825

Filename

5138825