Title :
Sequential redundancy removal using test generation and multiple unreachable states
Author :
Yotsuyanagi, Hiroyuki ; Hata, Shinsuke ; Hashizume, Masaki ; Tamesada, Takeomi
Author_Institution :
Dept. of Electr. & Electron. Eng., Tokushima Univ., Japan
Abstract :
In this paper, a procedure to reduce sequential circuits by removing undetectable faults in sequential circuits is proposed. To identify whether an undetectable fault is removable or not, strongly unreachable states, which are the states with no incoming transitions, are utilized. It is proved that part of undetectable faults related to strongly unreachable states can be removed from a circuit. Test generation method is used to find undetectable faults related to two or more strongly, unreachable states. Experimental results for ISCAS benchmark circuits are shown
Keywords :
automatic testing; fault diagnosis; integrated circuit testing; logic testing; redundancy; sequential circuits; ISCAS benchmark circuits; incoming transitions; multiple unreachable states; sequential redundancy removal; test generation; test generation method; undetectable faults; Benchmark testing; Circuit faults; Circuit testing; Combinational circuits; Fault diagnosis; Logic gates; Redundancy; Sequential analysis; Sequential circuits; Signal processing;
Conference_Titel :
Test Symposium, 2001. Proceedings. 10th Asian
Conference_Location :
Kyoto
Print_ISBN :
0-7695-1378-6
DOI :
10.1109/ATS.2001.990253
