Title :
Sub-0.25 /spl mu/m single N/sup +/-polycide gate CMOS technology for 2.5 V applications
Author :
Zhijian Ma ; Jeong Yeol Choi ; Chuen-Der Lien
Author_Institution :
Integrated Device Technol. Inc., San Jose, CA, USA
Abstract :
Sub-0.25 /spl mu/m gate length CMOS devices with N/sup +/ gate show excellent subthreshold characteristics and good suppression of short-channel effects such as punchthrough, V/sub T/ roll-off, DIBL and high-field effects. The CMOS devices are optimized by a trade-off between device driving capability and reliability. It should be pointed out that this 0.25 /spl mu/m CMOS technology using relatively thicker gate oxide (80 /spl Aring/) can be used in 3.3 V applications by further optimizing the device design and processes.
Keywords :
CMOS integrated circuits; integrated circuit technology; 0.25 micron; 2.5 V; DIBL; high-field effects; punchthrough; short-channel effects; single N/sup +/-polycide gate CMOS technology; subthreshold characteristics; threshold voltage roll-off; CMOS technology; Circuits; Length measurement; MOS devices; Robustness; Stress; Time measurement; Velocity measurement; Voltage; Voltage-controlled oscillators;
Conference_Titel :
Device Research Conference, 1996. Digest. 54th Annual
Conference_Location :
Santa Barbara, CA, USA
Print_ISBN :
0-7803-3358-6
DOI :
10.1109/DRC.1996.546297