Built-in self test using perturbed deterministic patterns

A built-in self-test method that applies perturbed deterministic patterns (PDPs) generated by an on-chip memory and compresses signatures on-chip is presented. The deterministic patterns are perturbed using a predefined algorithm. Software and hardware implementation in a level-sensitive-scan design environment are described. Using six industrial benchmarks as examples, it is shown that the PDP test generator provides an equivalent or better test coverage than a deterministic test generator or a pseudorandom pattern generator. The number of patterns to be stored is much smaller than when using deterministic patterns, while the number of PDPs to be applied to the device under test is much smaller than when using pseudorandom patterns