Implementing exhaustive self test using minimal cycle count and reduced area overhead

The problem of determining the number of cycles of test-pattern generation required to exhaustively test a block of logic is investigated, considering the case where the generator has more stages than the logic has inputs. Some statistical results are presented, and these are then compared with simulation results. The results show that it is easily possible to simulate the configurations used in current circuit designs. The results produced are exact and the cycle counts are typically 50% of those suggested by the statistical approach (for 0.999 probability of exhaustive testing). An example from a real chip which had a 14-bit generator feeding 56 testable units took only 48 s of CPU time to simulate