Title :
Hybrid BIST using partially rotational scan
Author :
Ichino, Kenichi ; Asakawa, Takeshi ; Fukumoto, Satoshi ; Iwasaki, Kazuhiko ; Kajihara, Seiji
Author_Institution :
Tokyo Metropolitan Univ., Japan
Abstract :
Developed a partially rotational scan (PRS) register used for the n-detection BIST (built-in self-test) that can detect not only delay faults but also unmodeled faults. The developed circuit consists of a shift register with partial rotation. Also presents a procedure for selecting test vectors from ATPG (automatic test pattern generation) ones. This testing method enables at-speed testing and the stuck-at fault coverage of n×100% by using subset of the ATPG vectors. And it drastically reduces the number of vectors input from an external low-speed tester. Computer simulations of stuck-at fault coverage are conducted on ISCAS´85, ISCAS´89, and ITC´99 circuits for detection times n of 1, 2, 3, 5, 10, and 15. They show that the compaction rates of the ATPG test vectors range from 52.4% (s713) to 0.9% (c499) of origin. This result demonstrates that the PRS register can accomplish low-cost, at-speed testing
Keywords :
automatic test pattern generation; boundary scan testing; built-in self test; combinational circuits; delays; fault diagnosis; integrated circuit testing; logic testing; sequential circuits; ATPG; ISCAS´85 circuits; ISCAS´89 circuits; ITC´99 circuits; at-speed testing; compaction rates; delay faults; external low-speed tester; hybrid BIST; n-detection BIST; partial rotation; partially rotational scan register; shift register; stuck-at fault coverage; test vectors; unmodeled faults; Automatic test pattern generation; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Computer simulation; Delay; Electrical fault detection; Fault detection; Shift registers;
Conference_Titel :
Test Symposium, 2001. Proceedings. 10th Asian
Conference_Location :
Kyoto
Print_ISBN :
0-7695-1378-6
DOI :
10.1109/ATS.2001.990313
