Title :
A practical logic BIST for ASIC designs
Author :
Sato, Y. ; Sato, M. ; Tsutsumida, K. ; Ikeya, T. ; Kawashima, M.
Author_Institution :
Device Dev. Center, Hitachi Ltd., Tokyo, Japan
Abstract :
Increasing number of pins or gates in the latest LSIs requires a lot of testing resources. The conventional scan-based testing requires a costly tester (ATE) equipped with a lot of pin electronics. Since reducing the testing cost is a crucial issue in industry, we have introduced an approach using scan-based logic BIST to solve this problem. The logic BIST has been applied to many ASIC design chips, which have up to several million gates
Keywords :
application specific integrated circuits; boundary scan testing; built-in self test; design for testability; large scale integration; logic testing; ASIC designs; DFT; LSI; logic BIST; scan-based testing; testing cost; testing resources; Application specific integrated circuits; Built-in self-test; CMOS logic circuits; Costs; Delay; Design for testability; Electronic equipment testing; Logic arrays; Logic design; Logic testing;
Conference_Titel :
Test Symposium, 2001. Proceedings. 10th Asian
Conference_Location :
Kyoto
Print_ISBN :
0-7695-1378-6
DOI :
10.1109/ATS.2001.990327
