Title :
A 942 MHz output, 17.5 MHz bandwidth, -70dBc IMD3 ΣΔ DAC
Author :
Luschas, S. ; Schreier, R. ; Lee, H.-S.
Author_Institution :
MIT, Cambridge, MA, USA
Abstract :
A DAC output controlled by an oscillating waveform is proposed to mitigate the effects of switching distortion and clock jitter. This architecture has the additional benefit of mixing the DAC impulse response energy to a higher frequency, allowing a high frequency image of the input to be used as the output. This saves power and hardware relative to a conventional transmitter architecture by eliminating the need for mixers and intermediate frequencies. The concept is demonstrated in a 1.8 V, 0.18 μm CMOS technology. The measured single-tone SFDR is 75 dB, SNR is 52 dB, and two-tone IMD3 is -70.8 dBc for a 17.5 MHz band centered at 942 MHz.
Keywords :
CMOS integrated circuits; digital-analogue conversion; integrated circuit design; sigma-delta modulation; timing jitter; transient response; ΣΔ DAC; 0.18 micron; 1.8 V; 17.5 MHz; 942 MHz; CMOS technology; SNR; clock jitter; impulse response energy; oscillating waveform controlled DAC output; single-tone SFDR; switching distortion; two-tone IMD3; Bandwidth; Clocks; Frequency domain analysis; Frequency synchronization; Intersymbol interference; Jitter; Nonlinear distortion; Sampling methods; Switches; Timing;
Conference_Titel :
Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003
Print_ISBN :
0-7803-7842-3
DOI :
10.1109/CICC.2003.1249376
