CMOS IC nanometer technology failure mechanisms

CMOS IC test targets are moving markedly with each nanometer technology node. Relatively stable defects, such as bridges and opens endure, but their detection is now often shrouded in a noisy environment with IC parameters that vary widely within the die, from die-to-die, wafer-to-wafer, or lot-to-lot. This variance in parameters introduces new concerns over failure mechanisms that laid mostly dormant for previous technologies. ICs can now fail from an "unlucky" distribution of parameters even though a defect is not present. Die-to-die reordering of critical timing paths is seen in modern ICs. This paper uses the defect-based approach to failure mechanisms that describes their electrical properties and then attempts to match a test method.