A capacitance method to determine the metallurgical gate-to-source/drain overlap length of submicron LDD MOSFETs

Author

Jo, Myung-Suk ; Kim, Jin-Hyoung ; Kim, Sung-Ki ; Yoon, Han-Sub ; Lee, Dai-Hoon

Author_Institution

Dept. of Electron. Eng., Kangnung Nat. Univ., South Korea

fYear

1995

fDate

22-25 Mar 1995

Firstpage

151

Lastpage

155

Abstract

A new CV method is proposed to determine the metallurgical gate-to-source/drain overlap length of LDD MOSFETs. In addition, the flatband voltage is extracted roughly by using the same method. The gate-to-substrate capacitances of a plate gate capacitor and finger type capacitor with the same total gate areas are measured with varying gate bias. At the peak point of difference between the two capacitor data, overlap length is extracted using a simple formula. This method is evaluated using the two-dimensional device simulator

Keywords

MOSFET; capacitance measurement; semiconductor device testing; capacitance measurement; finger type capacitor; flatband voltage; gate-to-substrate capacitance; metallurgical gate-to-source/drain overlap length; plate gate capacitor; submicron LDD MOSFETs; two-dimensional device simulator; Area measurement; Capacitance measurement; Capacitors; Data mining; Electrical resistance measurement; Fingers; Immune system; Length measurement; MOSFET circuits; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 1995. ICMTS 1995. Proceedings of the 1995 International Conference on

Conference_Location

Nara

Print_ISBN

0-7803-2065-4

Type

conf

DOI

10.1109/ICMTS.1995.513963

Filename

513963