Cluster growth technique for combinatorial evolvable digital circuits

The genetic algorithm (GA) is one of the optimization techniques of evolutionary algorithm used to design evolvable hardware. This paper proposes the application of cluster based growth approach with genetic algorithm for evolvable hardware. Earlier methods of evolving hardware proposed on static m × n grid structure of hardware that is evolved by reconfiguring interconnections. Clustering technique is a synthesis method where the hardware functionality is evaluated for minimum number of gates. The cluster grows by adding more gates into the cluster if the functionality is not obtained. Reconfiguration of interconnections is also preformed along with the cluster growth. Our main contributions are: 1) Adaptation of genetic operators in a way suitable for clustering growth. 2) Applications to task with unknown number of clusters in Clustering with genetic algorithm and demonstrate its performance. 3) To obtain the desired functionality with least number of logic gates such that the interconnection of nodes in the earlier defined architecture is modified with clustering, so that the fast convergence is obtained.