Neuron-MOS-based Dynamic Circuits for Multiple-Valued Logic

A neuron-MOS-based dynamic circuit scheme with two-phase clocks for realizing voltage-mode multiple-valued logic(MVL), is proposed. The dynamic ternary inverter, literal circuits, and quaternary inverter are designed, and the standard CMOS process with a 2-ploy layer is adopted without any modification of the thresholds. In the proposed circuits, the problem of floating output nodes is solved. The proposed circuits have some other favorable properties including the less complex structure, full logic swing and low propagation delay. All the proposed circuits are verified by HSPICE simulation results with TSMC 0.35μm 2-ploy 4-metal CMOS technology. For comparison, the energy consumption and the output delay of the proposed circuits are measured during the simulations.