Title :
A new IDDQ testing scheme employing charge storage BICS circuit for deep submicron CMOS ULSI
Author :
Lu, Chih-Wen ; Lee, Chung Len ; Chen, Jwu E. ; Su, Chauchin
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
In this work, a new IDDQ methodology, which is very suitable for testing deep submicron digital ULSI CMOS ICs, is proposed and demonstrated. It incorporates three new BICSs and has advantages of reduction in the circuit partitioning number, low input voltage, high resolution, low power supply voltage, and improved fault detectability and diagnosability
Keywords :
CMOS digital integrated circuits; ULSI; built-in self test; fault diagnosis; integrated circuit testing; logic testing; IDDQ testing scheme; charge storage BICS circuit; circuit partitioning number; deep submicron CMOS ULSI; fault detectability; fault diagnosability; input voltage; power supply voltage; resolution; Circuit faults; Circuit testing; Electrical fault detection; Electronic equipment testing; Histograms; Integrated circuit testing; Leakage current; Low voltage; Power supplies; Ultra large scale integration;
Conference_Titel :
IDDQ Testing, 1998. Proceedings. 1998 IEEE International Workshop on
Conference_Location :
San Jose, CA
Print_ISBN :
0-8186-9191-3
DOI :
10.1109/IDDQ.1998.730757
