Title :
A pipeline analogue to digital converter in 0.35 μm CMOS
Author :
Ross, S.W. ; Sinha, S.
Author_Institution :
Univ. of Pretoria, Pretoria
Abstract :
This paper describes an 8-bit, 130 MS/s pipelined analogue to digital converter (ADC) implemented in 0.35 μm CMOS technology from Austria Microsystems (AMS). The specifications for the design presented in this paper are in terms sampling frequency, power consumption, integral non-linearity (INL), differential non-linearity (DNL), signal to noise and distortion ratio (SNDR), and signal to quantization noise ratio (SQNR). The design achieved a SNDR of 47 dB corresponding to an effective number of bits (ENOB) of 7.5 bits. The system was designed to operate with a front-end working according to the Digital European Cordless Telecommunications (DECT) standard.
Keywords :
CMOS integrated circuits; analogue-digital conversion; integrated circuit design; Austria Microsystems; CMOS technology; design specification; differential nonlinearity; integral nonlinearity; pipeline analogue to digital converter; power consumption; signal to noise and distortion ratio; signal to quantization noise ratio; size 0.35 μm; terms sampling frequency; Analog-digital conversion; CMOS technology; Distortion; Energy consumption; Frequency; Pipelines; Quantization; Sampling methods; Signal design; Signal to noise ratio; Pipeline analogue to digital converter; dynamic comparator; sample and hold;
Conference_Titel :
EUROCON, 2007. The International Conference on "Computer as a Tool"
Conference_Location :
Warsaw
Print_ISBN :
978-1-4244-0812-2
Electronic_ISBN :
978-1-4244-0813-9
DOI :
10.1109/EURCON.2007.4400279
