50 kHz pattern recognition on the large FPGA processor Enable++

FPGA processors are very well suited for the implementation of image processing and pattern recognition tasks. This paper describes a particularly demanding application of this type and Enable++, the FPGA processor used. The system finds particle trades in high-energy physics detector images at a rate of 100 kHz. This requires to process a data stream of up to 500 MBytes/s in real time. The algorithm and the implementation on Enable++, a general purpose FPGA processor are described. Results from a software implementation are compared with the measurements from an implementation on the CCM. This implementation is 15 times faster than the software implementation on high end computers