Worst case analysis for evaluating VLSI circuit performance bounds using an optimization method

The process variations are unavoidable in today´s VLSI circuits due to the continuing scaled IC technologies, therefore, the likely behaviors of VLSI circuits with process variations may fail to meet the performance specifications. This paper addresses an efficient method to evaluate the performance bounds of VLSI circuits with process variations in time domain. The described approach proceeds by solving a Nonlinear Programming (NLP) problem to find the upper and lower bounds of the interested outputs, either a node voltage or a branch current, constrained by linearlized equations, circuit equations and parameter variations. The preliminary result shows the performance bounds from the proposed method are sufficiently tight comparing with the bounds obtained from intensive Monte Carlo samplings in SPICE.